Scaling of the ferroelectric field effect transistor and programming concepts for non-volatile memory applications

The importance of non-volatile memory for storage of digital information is without question. Research over the years has led to many different types of memory, each tailored to a specific need. Always, however, the search has continued for a universal type that combines high speed operation with non-volatility. One memory device with these properties is the ferroelectric Field Effect Transistor (FeFET), which is the object of study in this thesis. First, a short introduction to non-volatile memories is given. Then a comparison of the various alternatives is made which shows that the FeFET has a number of advantages compared to other non-volatile memory devices. Then the principles of operation of the FeFET are described based on the operation of the MOSFET and the ferroelectric capacitor. Using a transistor model and a mathematical algorithm for calculating the ferroelectric polarization, the FeFET model is derived. Further, the various challenges that the FeFET faces are elaborated. These include the depolarization field and the leakage current that leads to the reduction of the remnant polarization and as a result, to short data retention times. For the case of the leakage current, simulations are presented based on current transport mechanisms to estimate the boundaries of data retention time for the device. The miniaturization of the FeFET and comparison with the scaling of the MOSFET is considered next. Two scaling approaches are suggested, variable and constant gate stack scaling, of which the latter is applicable to even smaller dimensions than the former. As an alternative to physical miniaturization (dimension shrinking), multilevel cells (MLC) are discussed. Two programming concepts with FeFETs are then investigated. One uses negative gate erase and the other a positive voltage erase method. They are compared in terms of efficiency and ease of realization. The positive voltage erase concept does away with the need for a separate erase operation and simplifies the memory chip design. Finally, a 1-Kbit chip based on the positive voltage erase concept is introduced. The design and simulation were performed in schematic level. The memory design includes the FeFET matrix and peripheral electronics (decoders, voltage drivers, sense amplifiers). For the simulations a circuit simulator and a device simulator were deployed.

Grantor dc:publisher

Publikationsserver der RWTH Aachen University

Year dc:date

2005

Author dc:creator

• Fitsilis, Michael

Contributors dc:contributor

• Waser, Rainer

• info:eu-repo/classification/ddc/620
• Ferroelektrischer Transistor
• MOS-FET
• Speicherkarte
• Schaltungsentwurf
• FRAM <Informatik>
• Programmierung
• Ingenieurwissenschaften
• nicht-fluechtige Speicher
• ferroelektrischer Feldeffekttransistor
• Ferroelektrikum
• Chip
• non-volatile memories
• ferroelectric transistor

Statement dc:rights

• info:eu-repo/semantics/openAccess

Language dc:language

eng

Identifier

https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-123690%22

OAI identifier oai:identifier

oai:publications.rwth-aachen.de:62096