Modeling embedded processors and generating fast simulators using the machine description language LISA

Designers of new processors and software for systems-on-chip need a reliable design methodology and suitable tools to produce fast processor models which cover the relevant hardware details. This goal can be achived efficiently by employing formal processor descriptions using a suitable machine description language combined with retargetable and fast simulation tools being generated from such a formal processor description. This thesis presents the machine description language LISA (language for instruction-set architectures), its generic processor model and the fast retargetable processor simulator that can be generated from LISA descriptions. The language LISA enables the formal description of real embedded processors, their peripherals and interfaces. The development of this new language was necessary because existing languages are focused on either hardware or software properties. LISA uses the form of attributed grammars to combine hardware and software properties of a processor architecture in a joint description. These descriptions allow it to generate software development tools, such as simulators, assemblers and linkers. The behavioral model is completely specified in C which enables the reuse of legacy model components and makes the language intuitive to use. The language is completed by the generic machine model of LISA that is able to produce instruction-accurate, cycle-accurate and phase-accurate models based on control steps that implement a zero-delay model. Furthermore, the implementation of a retargetable environment is presented that produces compiled simulators from LISA processor descriptions. Using the LISA processor description significantly reduces the efforts of designing software development tools and makes processor specification transparent and understandable to others than the authors. Complete processor descriptions of real processor architectures such as the C62x DSP of Texas Instruments and the Analog Devices ADSP 21xx DSP are realized to prove the applicability of this approach. The expressive power of LISA is illustrated based on selected sections taken from these descriptions. Compiled simulators are generated from the processor descriptions and the models are successfully verified against our reference models. Measurements show that the simulation speed is up to two orders of magnitude higher than the speed provided by commercial simulators at the same accuracy level. The high simulation speed of the compiled technique helps to shorten the design cycles and improves the productivity of designers. The approach of formally describing processor architectures and generating the simulators as part of the development tools is successfully realized. It enables designers of processor architectures and software application code to evaluate their prototypes and reduces significant risks and consistency problems in the development of production-quality simulators.

Grantor dc:publisher

Publikationsserver der RWTH Aachen University

Year dc:date

2003

Author dc:creator

• Pees, Stefan

Contributors dc:contributor

• Meyr, Heinrich

• info:eu-repo/classification/ddc/004
• Eingebettetes System
• Mikroprozessor
• CASHE
• Codegenerierung
• Assembler
• Simulationssprache
• Informatik
• Simulation
• Prozessor
• Modell
• Maschinenbeschreibung

Statement dc:rights

• info:eu-repo/semantics/openAccess

Language dc:language

eng

Identifier

https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-120923%22

OAI identifier oai:identifier

oai:publications.rwth-aachen.de:59109