Advanced circuit design of gigabit density ferroelectric random access memories

The thesis deals with the circuit design of ferroelectric memory chips - called FeRAMs (ferroelectric random access memories). Regular circuits and techniques used in today's FeRAMs are examined for their suitability for use in future FeRAMs. New circuits and techniques are also presented. Some of these have been used in two memory chips which were developed within the framework of this thesis. The memory cell of a FeRAM is similar to one found in DRAM, since both use a capacitor to store information. In the case of FeRAM it is a ferroelectric and not a dielectric capacitor. Ferroelectric capacitors show hysteretic behavior between applied voltage and resulting charge. In an idle condition there are therefore two remanent polarization states which can be clearly differentiated. This property is used for the non-volatile storage of digital information. First, a simulation model for the ferroelectric capacitor is presented which was developed at the beginning of this work and implemented in a widespread circuit simulator (Cadence spectre TM) as a HDL model. The model is employed to investigate the effect of imprint on the memory operation. It permits the simulation of remaining signal voltage of a ferroelectric memory cell, which has been in the same polarization state for a very long time. The model was also integrated into two circuit simulators that are commercially available (HPSpice TM und HSIM TM). The main part of the thesis deals with the development of two ferroelectric memory chips. The first chip, a 0.35µm 512-kbit FeRAM consists half of a conventional FeRAM and half of a Chain FeRAM. This partitioning allows both types of memory architecture to be studied simultaneously. The Chain FeRAM architecture links several capacitors to a chain to increase the integration density and speed. The second chip is a 0.13µm 4-Mbit embedded FeRAM. ’Embedded’ means that the memory can be integrated with other circuits (e.g. a digital signal processor: DSP) on the same chip and does not require any process steps incompatible with the standard logic CMOS process. The memory cell occupies only 0.58 µm² and is to date the smallest FeRAM memory cell realized. The high integration density (~900 kbit/mm²) almost allows the realization of a Gigabit FeRAM. Moreover, this chip has a variety of new circuits and special functions, which allow the ferroelectric cell to be characterized in many respects. For instance, an operational mode reduces the time required to carry out the well-known fatigue test of the FeRAM storage cell. The test comprises 10 12 write accesses to the same cell and normally requires 2 - 5 days. The special mode only requires 6 hours for the same test. It also allows the execution of 10 14 test cycles which was not possible before. A further operation mode allows the measurement of the charge of all 4 million memory cells within the shortest time (~45 ms). This incredibly short period of measurement (as yet approx. 3 min.) could possibly form a basis for new methods of real-time characterization/calibration or quality control of ferroelectric chips. Finally, the thesis deals with the advantages and disadvantages of Chain FeRAMs and presents a simplified scaling theory for FeRAM.

Grantor dc:publisher

Publikationsserver der RWTH Aachen University

Year dc:date

2002

Author dc:creator

• Rickes, Jürgen Thomas

Contributors dc:contributor

• Waser, Rainer

• info:eu-repo/classification/ddc/620
• Ingenieurwissenschaften
• FeRAM
• ferroelectric memories

Statement dc:rights

• info:eu-repo/semantics/openAccess

Language dc:language

eng

Identifier

https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-120694%22

OAI identifier oai:identifier

oai:publications.rwth-aachen.de:58866